The Interface Board sits logically between the Samplers and the Adlink Board.
- Drive the 32 bits of the sampled data down a SCSI cable 10m (max) to the Adlink Board
- Registers provided for initial settings such as sampling rate
- Acts as a path to set registers on external devices such as the samplers and the Local Oscillators
- Allows for precise synchronisation to the Station Clock pulses so that timing accuracy is assured
- Produces header information to allow for data error detection
- Four test modes available for transmission rate evaluation
Adlink SCSI Signals Relevent to COBRA
The following table is an extract from the Adlink manual. The data direction sense is that as seen by the Adlink card. i.e. I is from Interface board to Adlink board.O is from Adlink Board to Interface Board.
|Signal Name||Signal Type||Signal Direction||Description|
|PB(15:0)||DATA||I/O||PortB bidirectional data lines-PB15 is the MSB, and PB0
is the LSB.|
|PA(15:0)||DATA||I/O||PortA bidirectional data lines-PA15 is the MSB, and PA0 is the LSB.|
|AUXDO(3:0)||DATA||O||AUX DO 3
0 can be used as extra output data or can be used as extra control signals.|
|AUXDI(3:0)||DATA||I||AUX DI 3
0 can be used as extra input data or can be used as extra control signals.|
|DI-REQ||CONTROL||I||Request line In external clock mode, DI-REQ carries the external clock input.|
|DO-REQ||CONTROL||O||Request line In handshaking mode, DO-REQ carries handshaking control information to peripheral.|
|DO-ACK||CONTROL||I||Digital output Acknowledge lines In handshaking mode, DO-ACK carries handshaking status information from the peripheral.|
Data Lines used as Control Signals
Two Auxilary signals output from the Adlink board have been used to control the interface board
|Adlink Signal Name||Alias||Function|
|AUXDO0||ARM||When HIGH sampling or test mode will commence on the following 10 seconds
|When LOW sampling or test mode will cease
|AUXDO1||DIRECTION||When HIGH data flow is from Interface to Adlink (SAMPLING Mode)
|When LOW data flow is from Adlink to Interface (INITIALISATION Mode)
Data from the Samplers When DIRECTION = 1 (SAMPLING Mode)
Ports PA(15:0) and PB(15:0) have been used as follows:
- RI is Right Hand In-phase
- RQ is Right Hand Quadrature
- LI is Left Hand In-phase
- LQ is Left Hand Quadrature
Data flow is controlled by the interface in a non-handshaking mode. Refer to the Adlink manual, section 4.10.2 "Digital Input DMA in External Clock Mode" Data is clocked into the Adlink board on the rising edge of the DI-REQ signal.
Data from the Adlink Board When DIRECTION = 0 (INITIALISATION Mode)
For this mode to function, the toggle switch on the front of the board must be in the "remote" setting.
In this mode, only 16 bits are used, PB(0:16).
- A is an 8-bit address code pointing to a register
- D is an 8-bit data word to go into the specified register
Data flow is controlled by the Adlink Board in a handshaking mode. This is because there are some time sensisitve registers to be filled. The Interface Board, "handshakes" when data is latched. Refer to the Adlink manual, section 4.11.2 "Digital Output DMA in Handshaking Mode." Data is clocked onto the Interface Board on the rising edge of the DO-REQ signal, as generated by the Adlink Board. The Interface Board acknowledges receipt of data by asserting the DO-ACK line.
The interface board has on-board registers which control sampling rate, and determine which of the two samplers is active.
The interface board also acts as a channel to program the following:
The programming of the Interface Board is by one of two means.
- Adjacent two Sampler Board attenuator settings and frequency channel
- Frequency setting of LO's associated with Sampler Boards
A toggle switch selects between these two modes, and if this is set to Manual, all INITIALISATION commands from the DMA interface will be ignored!
When DIRECT=0 it is possible to program all the available registers in the Interface, the Samplers, and the LO's. In the following table every bit-wise flag is shown, firstly its location, and in following tables, the functionality.
Manual: DIP switches on the front of the Interface Board may be used to program the initial settings of all registers. There are two sets of eight DIP switches, one set acts as ADDRESS, and the other as DATA. A push button "Enters" the DATA onto the selected ADDRESS.
- Remote: Similar to Manual Mode, but DATA and ADDRESS information is sent over the data cable from the DMA interface board.
|Sampler 0 Register||0||0||0||0||0||0||0||0||-spare-||BANDSW||ATTR3||ATTR2||ATTR1||ATTL3||ATTL2||ATTL1|
|Sampler 1 Register||0||0||0||0||0||0||0||1||-spare-||BANDSW||ATTR3||ATTR2||ATTR1||ATTL3||ATTL2||ATTL1|
|Interface Register A||0||0||0||0||0||0||1||0||-spare-||-spare-||-spare-||SAMPLER1||SAMPLER0||SPEED2||SPEED1||SPEED0|
|Interface Register B||0||0||0||0||0||0||1||1||-spare-||-spare-||-spare-||-spare-||-spare-||-spare-||-spare-||-spare-|
|LO0 Frequency Register||0||0||0||0||0||1||0||0||FREQ7||FREQ6||FREQ5||FREQ4||FREQ3||FREQ2||FREQ1||FREQ0|
|LO1 Frequency Register||0||0||0||0||0||1||0||1||FREQ7||FREQ6||FREQ5||FREQ4||FREQ3||FREQ2||FREQ1||FREQ0|
BANDSW selects between the two available frequency bands on the specific sampler as follows:
ATTL(3:1) sets the left hand attenuation, and ATTR(3:1) the right. This is a logical relationship as shown below:
SAMPLER(1:0) determines which of the two Samplers are selected. It is important to set these correctly to avoid corrupt data:
|0||0||No Samplers selected, (only used for test modes)|
|0||1||Only Sampler 0 selected|
|1||0||Only Sampler 1 selected|
|1||1||Both Samplers 0 & 1 selected|
SPEED(2:0) sets the Sampling Rate and data transmission rate of the machine as follows:
|SPEED2||SPEED1||SPEED0||Sampling Rate Mega Samples per sec||Transmission Rate Mega bytes/ sec
Header Word Generation
Once each second two header words are produced in the data. This appears in the place of sampled data following the rising edge of the station 1PPS signal. The following tables describe the words transmitted. Briefly, there are flag words, a count word and identifier words. Note that this is not produced in the test modes.
| ||Word 2
- c is one bit of the Counter Word
- ID is one bit of the Interface Board Identifier Word
When the three SPEED bits in the Interface Register are set to 100 ; 101 ; 110 ;or 111 the Interface Board enters a test mode state. The board produces 32 bits of count word incrementing at 5,10,20 and 40 Million Bytes per second. This runs continuously while the two control bits (AUXO0, and AUXO1) are asserted.
Sampling Mode Sequence of Operation
When all registers are correctly set, either by DIP switches or Remote Control, sampling may begin. This is done by setting DIRECTION=HIGH, and ARM=HIGH. Sampling will commence synchronously with the following round ten second. The first two words to be transmitted will be the two 32 bit header words as described. Following this will be the data. One 32 bit word is transmitted per sample period per sampler board selected. SAMPLER0 data is transmitted first then SAMPLER1 data. This will continue until the next 1PPS, when the header words will again be transmitted. This state will continue until ARM is cleared to low.
LED's on the front of Interface Board
Subject to change to make a more logical display!
|(ARM AND DIRECTION)|
Written by Tim Ikin on 27th February 2002
Modified by Tim Ikin on 24th May 2002